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Introduction

Achievement of proper and reliable solder joints in electronic equipment depends on many constructional and technological factors including an adequate level of solderability of elements to be jointed, i.e. components and printed boards.
The most common method of solderability protection of printed boards is coating the conductive copper pattern with Sn–Pb alloy layer almost eutectic in composition. The majority of PCBs produced are coated with HASL deposit. HASL’s dominance has continued over the past several years despite its serious technical limitations [1]. Boards manufactured in such a way, in spite of their solderability protected during storage are not suitable for all applications. Thus: fine pitch VLSI electronic components used in SMT require excellent planarity of solder pads on PCBs [2]. The requirement of planarity is not met by conventional HASL finish [3]. Example of this problem solution may be the following lead–free finishes:

• electroless, autocatalytic Ni/immersion Au,
• electroless, matt Sn, OrmeconÒ CSN,
• organic solderability preservative, Enthone^TM

Entek Plus.

Apart from already quoted features these finishes must exhibit good solderability after manufacturing as well as after storage. Besides this the finishes should be compatible with alloys and fluxes used in electronics.

2. Solderability testing

Fig.2. Test specimen

Eutectic alloy solder bath 63Sn37Pb at temperature of 250°C and no–clean, low–solid, mildly activated fluxes have been applied for the testing. For Ni/Au finish TZ-3/ITR flux (based on organic esters of dicarboxylic acids and activated by dicarboxylic acid and organic salt) has been used and for Sn–Pb HASL, Sn OrmeconÒ , OSP Entek Plus coatings TN/4A/ITR flux (based on organic esters of dicarboxylic acids and activated by blend of dicarboxylic acids) was chosen.

For solderability testing the Meniscograph Solderability Tester type MK^6A hooked up to a computer has been used. Solderability tester set-up diagram is shown in Fig.3.

Fig.3. Solderability tester set – up diagram

PCBs solderability criteria and requirements are presented in the Table 1 as in ANSI/J–J–STD–003 [9]:

• Wetting time t _z [s] – time counted from the moment at which the specimen and solder bath first make contact till the moment when the contact angle is equal to 90° (only the buoyancy force acts on the specimen and the non – wetting state passes into the state of wetting).

• Max. wetting force P_max [mN/m] – it is the measured force F_max [mN] per borderline unit (metallic part only) between specimen and solder.

• Solder coating quality of the immersed surface estimated visually after withdrawal of the specimen from the solder bath.

3. Solderability test results

The test results: wetting time t _z and wetting force P_max are presented in the Table 2.

Table 2. The wetting balance test results

Solder coating quality of this specimen parts that were immersed in the soldering bath have been examined visually. It has been stated that all boards under tests, irrespective of the type of finish and the state of PCB’s had been coated with bright, smooth, continuous and shining Sn63Pb37 solder layer without dewetting. The exception to this rule is OSP Enthone^TM Entek Plus after conditioning at 155°C, 4 h; non – wetting and dewetting surface is more than 90%.

Fig.4. The wetting balance curves of PCBs with different finishes in the state "as received"

Solderability test results show that:

• all finishes under test exhibit good solderability level, because wetting force P_max. > 120 mN/m, wetting time t _z < 2 s and surfaces are covered with bright, smooth, continuous and shining solder layers without dewetting both in PCBs state "as received" and after natural and accelerated ageing,

2. Surface Insulation Resistance Tests

Surface Insulation Resistance (SIR) method [12, 13] is a quantitative method of assessment of electrical properties of insulation materials including surface resistance between conductive pads on PCBs. SIR of PCBs is affected also by the finishing technology.

The test specimens (Fig.7) were made of 1.5 mm epoxy-glass FR- 4 laminate, single sided with 18 m m copper foil and then they were adequately covered with the tested finishes (see sub-close 2.1). For comparison purposes there has also been carried out a test with "bare" copper boards.

For SIR tests the a -Metals Sirometer Model 300, software version 2.6 hooked up to a computer has been used. At first SIR has been measured under normal environmental conditions. Then the specimens were conditioned in a humidity chamber. At the first stage of conditioning in the humidity chamber the temperature was equal to 85°C and relative humidity (RH) 20%. After 3 h of stabilising the humidity slowly ramped up to 85% and the specimens have been allowed to reach equilibrium during one hour. Next the bias voltage +50V DC was applied for a period of 168 h. The measurements were carried out with 24 hour intervals. For the SIR measuring a voltage of –100V DC was used.

The "comb pattern" test specimens meet requirements concerning surface insulation resistance ANSI/J–J–STD–004 [14] if after 96 h and 168 h conditioning in the humidity chamber SIR value is at least 100 MW . The SIR test results are presented in Table 3 and Fig.8.



Fig.7. IPC-B24 "comb pattern" specimen

Finish type	log SIR [W ]
	Conditioning time in humidity chamber [h]
	0	24	48	72	96	168
Cu any coating	12.0	11.2	11.3	11.3	11.0	11.0
Sn-Pb HASL	11.4	11.3	10.5	10.2	10.2	10.3
electroless Ni /immersion Au	11.9	11.0	11.2	11.2	11.4	11.4
electroless Sn Ormecon Ò CSN	10.4	9.7	10.7	10.7	10.5	10.1
OSP EnthoneTM Entek Plus	12.0	10.4	10.7	11.2	11.0	10.8

Table 3. Surface insulation resistance



Fig.8. SIR curves

The results show that all the specimens under test meet SIR requirements that means: none of the investigated finish technology has a negative influence on surface insulation resistance of PCBs.

3. Shear Strength of Soldered Joints

Chip 1206 resistors have been soldered on PCB pads by an IR reflow process according to temperature profile as in Fig.9, using SnPbAg "fine – pitch" solder paste.

Shear strength of soldered joints have been assessed after reflowing process and after conditioning at 145°C, 220 h. The shear force was applied to the resistor in the middle of its longer side, in parallel to the PCB surface, until destruction of the joint. The rate of force increasing was constant and equal to 20 N/s. The test results are presented in Table 4.

Table 4. Results of shear strength test

• OSP Enthone^TM Entek Plus only is not resistant against long – term, high temperature action.

• In the "as received" state finishes: Sn – Pb HASL, Sn OrmeconÒ CSN and OSP Enthone^TM Entek Plus have comparable solderability and Ni/Au coating is characterised by a little lower solderability.
• Natural and accelerated ageing decrease, but not reduce below required level, solderability of PCBs covered by investigated finishes.
• All of investigated finish technologies have no negative influence on surface insulation resistance of PCBs.
• Shear strength of soldered joints is more or less comparable for all coatings.
• PCBs with all presented lead–free finishes are a good alternative to PCBs with Sn–Pb conventional finish for SMT applications.

Acknowledgements

Mr. J.Sitek for their help with preparation of samples, carrying out the measurements and data plotting.

References

Fig.5. Diagram of solderability change–max wetting force P_max after different conditionings

Fig.6. Diagram of solderability change – wetting time t _z after different conditionings

Ormecon Chemie GmbH & Co. KG
- a subsidiary of Zipperling Kessler & Co. (GmbH & Co.) -
Ferdinand-Harten-Str. 7 • D-22949 Ammersbek • Tel.: +49-(0)40-604106-0 • Fax: +49-(0)40-604106-51

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